Este es el codigo:

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.numeric_std.all;

use IEEE.std_logic_unsigned.all;

entity preg1 is

port

(a,b,c : in std_logic_vector (3 downto 0);

x,y,z : out std_logic_vector (2 downto 0);

m : out std_logic);

end preg1;

architecture errores of preg1 is

begin

with a select

m <= '0' when "0000" ,

<= '1' when "0101" ;

b <= a and (not c);

y <= "001" when a=b else "111";

end errores;

Estos son los errores:

ERROR:HDLParsers:164 - "D:/VHDL/Lab/preg1.vhd" Line 18. parse error, unexpected LE

ERROR:HDLParsers:1402 - "D:/VHDL/Lab/preg1.vhd" Line 19. Object b of mode IN can not be updated.

AYUDA URGENTE !!!