logic gates?
if a signal passing through a gate is inhibited by sending a LOW into one of the inputs and the output is HIGH the gate is a(n)
a. and
b. nand
c. or
d. nor
what does it mean for a signal to be inhibited mean?
More Questions From This User See All
Answers & Comments
Verified answer
First, when one input of an AND gate is low the output is defined and therefore the other inputs become irrelevant, ie inhibited.
Next, if the low input forces the output high then the gate includes inversion, ie it is a NAND gate.
In this context, I would read it to mean that it renders the input irrelevant. Nothing happens when the input changes.
So you have
L L => H
L H => H
The only gate this is consistent with is NAND.